A variable gain amplifier (VGA) is used in a wide range of communication systems. Due to its frequent use in a variety of situations, it is desirable for a VGA to have features in order to maintain a good dynamic range across a full gain control range. For example, desirable characteristics of a VGA include high linearity, low noise, low DC power consumption, linear-in-dB gain control, high frequency operation, and gain setting independent of temperature.
FIG. 1 (Prior Art) illustrates a conventional multi-stage VGA 100. The VGA 100 receives inputs +Vin/2 and −Vin/2 and provides outputs Iout+ and Iout−. The inputs are applied to the bases of transistors 10 and 36, respectively, which have their emitters coupled to ground through respective current sources. Connected in series between transistor 10 and ground are resistors 24-34 and a current gain control (GC) 24. Connected in series between transistor 36 and ground are resistors 48-58 and a different current gain control 72.
Connected between Iout+ and Iout− are six differential pairs of transistors. The emitters of a first differential pair of transistors 10 and 46 are connected together. The emitters of a second differential pair of transistors 12 and 44 are connected together. The emitters of a third differential pair of transistors 14 and 42 are connected together. The emitters of a fourth differential pair of transistors 16 and 40 are connected together. The emitters of a fifth differential pair of transistors 18 and 38 are connected together. The emitters of a sixth differential pair of transistors 20 and 36 are connected together. Each of the transistor emitters has a tail current source. For example, the first differential pair has a tail current source 60. The second differential pair has a tail current source 62. The third differential pair has a tail current source 64. The fourth differential pair has a tail current source 66. The fifth differential pair has a tail current source 68. The sixth differential pair has a tail current source 70.
The base of transistor 12 is connected to the junction between resistors 24 and 26. The base of transistor 14 is connected to the junction between resistors 26 and 28. The base of transistor 16 is connected to the junction between resistors 28 and 30. The base of transistor 18 is connected to the junction between resistors 30 and 32. The base of transistor 20 is connected to the junction between resistors 32 and 34. The base of transistor 38 is connected to the junction between resistors 48 and 50. The base of transistor 40 is connected to the junction between resistors 50 and 52. The base of transistor 42 is connected to the junction between resistors 52 and 54. The base of transistor 44 is connected to the junction between resistors 54 and 56. The base of transistor 46 is connected to the junction between resistors 56 and 58.
Input voltages +Vin/2 and −Vin/2 are delivered to the bases of the transistors 10-46 in different versions that are shifted in accordance with the voltage drops across resistors 24-58. If the resistances of all resistors are equal (R), an offset voltage exists between the bases of each differential pair of transistors. The offset for the first pair is equal to the difference between the input voltage at the base of transistor 10 and the voltage drops across the five resistors 48 through 56, or proportional to 5×R. The offsets for the second through sixth pairs are proportional to 3×R, R, R, 3×R and 5×R, respectively. The offset for each pair is designated to be Ri, wherein i represents the number of the differential pairs.
With zero gain control currents in the resistor paths, all differential pairs operate without any offset and maximum gain is obtained. Increasing the gain control current will produce different offsets across the individual pairs, thereby downwardly adjusting the gain. The gain with respect to control current is represented by the following relationship:
                                                        I              out                        ⁡                          (                              V                in                            )                                =                                    α              F                        *                          I              ptat                        *                                          ∑                                  i                  =                  1                                n                            ⁢                              tanh                ⁢                                                                            V                      in                                        -                                          φ                      i                                                                            2                    ⁢                                                                                  ⁢                                          V                      T                                                                                                          ⁢                                  ⁢                                                            φ                i                            /                              (                                  R                  ·                  GC                                )                                      =                          n              -              1                                ,                      n            -            3                    ,          …          ⁢                                          ,                      -                          (                              n                -                3                            )                                ,                      -                          (                              n                -                1                            )                                      ⁢                                  ⁢                                  ⁢                                            for              ⁢                                                          ⁢              i                        =            1                    ,          2          ,          …          ⁢                                          ,                      n            -            1                    ,          n                                    (        1        )            Where Iptat is the differential pair tail current, αF is the ratio between the collector and emitter current of the corresponding transistors, VT is the thermal voltage, and ψi is the DC offset of the differential pair i. The transconductance can be derived by differentiating Iout with respect to Vin.
                              gm          ⁡                      (                          V              in                        )                          =                                                            α                F                            *                              I                ptat                                                    2              ⁢                              V                T                                              *                                    ∑                              i                =                1                            n                        ⁢                          sec              ⁢                                                          ⁢                              h                2                            ⁢                                                                    V                    in                                    -                                      φ                    i                                                                    2                  ⁢                                      V                    T                                                                                                          (        2        )            FIG. 2 shows plots of transconductance of VGA 100 with respect to the input voltage, wherein the X axis represents the input voltage and the Y axis represents gm. Different curves 205, 210, 215, 220, 225, and 230 correspond to gm measured with respect to different gain control currents (GCs). The most sharp curve corresponds GC=0. The curve marked with a diamond symbol corresponds to GC=60. The curve marked with a downward triangle symbol corresponds to GC=120. The curve marked with a upward triangle symbol corresponds to GC=180. The curve marked with a square symbol corresponds to GC=240. The curve marked with a “+” symbol corresponds to GC=300. As the gain control current GC increases, gm decreases or the gain becomes smaller. In addition, when gm decreases, gm is linear across a wider range of input voltage. That is, the linearity of the VGA 100 improves as the gain is lower.
In the VGA 100, the resistors 24-58 present along the signal path may significantly degrade the VGA's performance. For example, the bandwidth and the high frequency operation of the VGA may be negatively affected. In addition, the presence of these resistors may degrade the noise performance of the VGA 100. Even though the bandwidth of the VGA 100 may be compensated by employing a low resistance and a high GC current, the high degree of noise caused by the high GC current may degrade the VGA's performance. Furthermore, the high GC current also increases the DC power consumption, which is undesirable. This is shown in FIG. 3a, which shows the VGA's gain and its input referred noise with respect to frequency under different control currents. In FIG. 3a, the X axis represents frequency. The Y axis of the upper portion of FIG. 3a represents the amplitude of the noise. The Y axis of the lower portion of FIG. 3a represents the amount of gain measured. Different curves in each plot correspond to different gain control current. The top curve marked with a square symbol corresponds GC=0. The curve marked with a diamond symbol corresponds to GC=60. The curve marked with a downward triangle symbol corresponds to GC=120. The curve marked with a upward triangle symbol corresponds to GC=180. The curve marked with a square symbol corresponds to GC=240. The curve marked with a “+” symbol corresponds to GC=300. As can be seen, when the control current is higher, the VGA's gain decreases. When the frequency increases, the VGA's gain also decreases.
In addition, the VGA's performance is also affected by temperature. As evident from equation (2), transconductance is a function of thermal voltage VT, which varies with temperature. VT is an element in the denominator of two parts of the gain equation. Thus, in the known amplifier gain stage of FIG. 1, gain is variable with temperature. FIG. 3b shows plots of linearity-in-dB and gain with respect to gain control current GC. The linearity error and the gain are relatively linear in the central range, of approximately 0.4 m to 0.6 m, while having an increasing error in linearity through the range above 0.6 m. The plot of linearity-in-dB exhibits curvature, the extent of which can be appreciated in FIG. 3b. To have a VGA that maintains quality high frequency operation, high linearity, low DC power consumption, linear-in-dB gain control, and robust performance against noise, and gain setting independent of temperature, an improved VGA is needed.